This invention relates generally to electronic devices, and more specifically to manufacturing methods and structures that improve semiconductor device performance.
In the processing of integrated circuit (IC) devices, yield is a key economical parameter that IC manufacturers pay close attention to. Poor yielding devices impact, among other things, manufacturing cycle time, resource allocation, on-time delivery, market share, and profits. Excessive or high leakage current is often one parameter that causes poor yields in IC manufacturing. High leakage current is typically caused by the presence of fast diffusing impurities or defects in active device regions within a semiconductor substrate.
One known method of reducing this problem is referred to as extrinsic gettering, which is a process to remove the unwanted impurities from critical regions of IC devices and thereby reduce the formation of impurity related defects. In a typical extrinsic gettering process, one or more polycrystalline semiconductor layers are deposited on the back or lower surface (i.e., the surface opposite the surface where active devices are formed) of a monocrystalline semiconductor wafer prior to any high temperature process. The presence of the polycrystalline layer induces stress on the semiconductor wafer, which acts to getter or remove the unwanted impurities during subsequent high temperature processing and to reduce the formation of impurity related defects. Unfortunately, during the subsequent high temperature process steps, the polycrystalline silicon layer itself recrystallizes, and thus loses a significant part of its gettering capability.
In addition, the polysilicon layer(s) can induce compressive stress on the semiconductor wafer, which can cause the semiconductor wafer to warp. This warpage issue can result in breakage and other quality issues particularly as the wafer diameter increases and/or the wafer thickness decreases.
A further problem associated with wafer processing involves the formation of semiconductor material aggregates referred to as silicon nodules. These defects grow on the lower surface of the wafers during, for example, the deposition of epitaxial layers. Typically, the nodules grow on the wafer when a low temperature oxide (LTO) is used as a backside sealing layer. The nodules are approximately spherical in shape, and can have diameters up to 40 microns. Defects of that size have caused wafer processing issues, including, for example, vacuum leak issues when the wafers are placed on vacuum support chucks. The vacuum leak issues can lead to misprocessed wafers, such as poorly transferred images in photolithography process steps.
Accordingly, an improved method and structure are needed that provide, among other things, gettering capability, reduced wafer warpage, and reduced formation of other defects, such as nodules. It would be further beneficial if such a method and structure were cost effective, were accomplished using existing equipment with minimal wafer transfers between equipment, and were to avoid added wafer clean steps.